1. Field of the Invention
SRAM access time can be dominated by the bit line swing in large SRAMs. The present invention relates to embedding multiple sense amps into the SRAM core with the SRAM cells and interconnecting the sense amps over the array, thereby reducing the effective bit line length and improving access time significantly.
2. Description of the Prior Art
SRAMs consist of an array of SRAM cells. To access a given set of cells, a given word line is activated which is connected to every SRAM cell in a given row. Depending on the state of the SRAM cell, an activated SRAM cell either pulls charge out of the true or complement column lines which are referred to as bit lines. The bottom of the array consists of sense amplifiers that are connected to the differential bit lines and which sense and amplify the resultant signal from the SRAM cells. Various multiplexing schemes both before and after the sense amps reduce the data output width to the desired size.
Particularly in large SRAMs, where there are many rows of SRAM cells (e.g., over 100), the slew rate on the bit lines is very slow. This is because the capacitance on the bit lines is high and the SRAM cell current is small and, hence, the access time is poor.
There are three standard techniques for improving the bit line slew rate:
1. Increase the cell current. This must be accomplished without increasing the cell size significantly or the improved current will have a larger capacitance to drive, which will nullify its effect. PA1 2. Reduce the number of cells on the bit line by reducing the number of rows in the array. The desired SRAM size can then be preserved either by increasing the number of columns and muxing or by building multiple banks of SRAM cells and muxing the results together. PA1 3. Reduce the signal swing required for the sense amp to accurately sense the bit lines.
Approaches (1) and (3) have been applied successfully over many generations of relatively small SRAMs. For large, fast SRAMs, approach (2) has recently also been used. In particular, most large, fast SRAMs employ multiple small banks to achieve their faster access times.
Multiple banks of smaller SRAMs, however, have a set of problems. Muxing the banks together increases the overhead of the periphery circuitry and adds to the access time, partially negating the increased access time of the individual banks. Some of the muxing and wiring can be eliminated in the banked approach by muxing the output of each bank down to a single output bit, for example. However, this requires each bank to be accessed on every cycle, thus greatly increasing the power consumption of the overall SRAM.